Technical documents
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number of Channels
1
Schmitt Trigger Input
Yes
Input Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
5 ns @ 5 V
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Temperature
-40 °C
Propagation Delay Test Condition
50pF
Height
0.9mm
Maximum Operating Temperature
+85 °C
Length
2mm
Width
1.25mm
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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₪ 6.796
Each (Supplied on a Reel) (ex VAT)
₪ 7.951
Each (Supplied on a Reel) (inc VAT)
5
₪ 6.796
Each (Supplied on a Reel) (ex VAT)
₪ 7.951
Each (Supplied on a Reel) (inc VAT)
5
Buy in bulk
quantity | Unit price | Per Reel |
---|---|---|
5 - 20 | ₪ 6.796 | ₪ 33.98 |
25 - 45 | ₪ 5.664 | ₪ 28.32 |
50 - 95 | ₪ 5.244 | ₪ 26.22 |
100 - 245 | ₪ 5.006 | ₪ 25.03 |
250+ | ₪ 4.699 | ₪ 23.49 |
Technical documents
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number of Channels
1
Schmitt Trigger Input
Yes
Input Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
5 ns @ 5 V
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Temperature
-40 °C
Propagation Delay Test Condition
50pF
Height
0.9mm
Maximum Operating Temperature
+85 °C
Length
2mm
Width
1.25mm
Minimum Operating Supply Voltage
1.65 V
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22