Technical documents
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Bus Transceiver
Number of Elements per Chip
2
Number of Channels per Chip
16
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
48
Input Level
LVTTL
Output Level
LVTTL
Maximum High Level Output Current
-24mA
Maximum Low Level Output Current
24mA
Maximum Propagation Delay Time @ Maximum CL
4.7 ns @ 2.7 V
Minimum Operating Supply Voltage
1.65 V
Height
1.15mm
Width
6.1mm
Minimum Operating Temperature
-40 °C
Dimensions
12.5 x 6.1 x 1.15mm
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
12.5mm
Maximum Operating Supply Voltage
3.6 V
Product details
74LVC Family Bus Transceivers, Nexperia
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
₪ 327.36
₪ 10.56 Each (In a Tube of 31) (ex VAT)
₪ 383.01
₪ 12.355 Each (In a Tube of 31) (inc. VAT)
31
₪ 327.36
₪ 10.56 Each (In a Tube of 31) (ex VAT)
₪ 383.01
₪ 12.355 Each (In a Tube of 31) (inc. VAT)
31
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Please check again later.
quantity | Unit price | Per Tube |
---|---|---|
31 - 124 | ₪ 10.56 | ₪ 327.36 |
155+ | ₪ 8.19 | ₪ 253.89 |
Technical documents
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Bus Transceiver
Number of Elements per Chip
2
Number of Channels per Chip
16
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
TSSOP
Pin Count
48
Input Level
LVTTL
Output Level
LVTTL
Maximum High Level Output Current
-24mA
Maximum Low Level Output Current
24mA
Maximum Propagation Delay Time @ Maximum CL
4.7 ns @ 2.7 V
Minimum Operating Supply Voltage
1.65 V
Height
1.15mm
Width
6.1mm
Minimum Operating Temperature
-40 °C
Dimensions
12.5 x 6.1 x 1.15mm
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
12.5mm
Maximum Operating Supply Voltage
3.6 V
Product details
74LVC Family Bus Transceivers, Nexperia
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS